The software application published by Aldec that includes the feature or module called **RIVIERA_VERILOG_SIMULATION** is **Riviera-PRO**. Rivera-PRO is a sophisticated simulation and debug environment for Verilog, VHDL, and SystemVerilog.
**RIVIERA_VERILOG_SIMULATION** refers to the capability within Riviera-PRO that specifically handles the simulation of Verilog designs. This module allows users to perform simulation tasks on Verilog code,