which software application published by 'Aldec' has a feature/module/file called 'RIVIERA_VHDL_SIMULATION? What is RIVIERA_VHDL_SIMULATION?

RIVIERA_VHDL_SIMULATION is a component of Aldec's **Riviera-PRO** software, which is a comprehensive simulation tool for VHDL and other HDLs (Hardware Description Languages). Riviera-PRO is primarily used in the design and verification of digital systems, particularly in FPGA and ASIC development. The RIVIERA_VHDL_SIMULATION module specifically provides capabilities for VHDL simulation, allowing engineers to simulate and validate their VHDL designs before moving on to synthesis and implementation. It supports various simulation methodologies, including functional and timing simulations, and features advanced debugging tools, assertions, and testbenches. Overall, Riviera-PRO with RIVIERA_VHDL_SIMULATION enables users to effectively test and verify the behavior of their VHDL code, ensuring that designs meet specifications and function correctly in the intended applications.