The software application published by Aldec that includes the feature or module called 'RIVIERA_VERILOG_SIMULATION_LV' is **Riviera-PRO**. This is a powerful simulation and verification tool for digital designs that supports various hardware description languages, including Verilog, VHDL, and SystemVerilog.
**RIVIERA_VERILOG_SIMULATION_LV** specifically pertains to the simulation capabilities for Verilog designs within the Riviera-PRO