which software application published by 'Aldec' has a feature/module/file called 'RIVIERA_VERILOG_SIMULATION_LV? What is RIVIERA_VERILOG_SIMULATION_LV?

The software application published by Aldec that includes the feature or module called 'RIVIERA_VERILOG_SIMULATION_LV' is **Riviera-PRO**. This is a powerful simulation and verification tool for digital designs that supports various hardware description languages, including Verilog, VHDL, and SystemVerilog. **RIVIERA_VERILOG_SIMULATION_LV** specifically pertains to the simulation capabilities for Verilog designs within the Riviera-PRO environment. This module enables users to run simulations of their Verilog code, providing features such as: - Advanced debugging tools - Performance optimization - Comprehensive reporting - Support for mixed-language simulations - Integration with various design flows and environments Overall, it is an integral part of the Riviera-PRO suite, designed to enhance the simulation and validation processes for Verilog-based designs.