The software application published by Aldec that includes a feature or module called `RIVIERA_PROFILER_VIEWER_SUPP` is **Riviera-PRO**. This is a comprehensive simulation and debug tool used widely in the field of electronic design automation (EDA), mainly for the development and verification of digital systems. The `RIVIERA_PROFILER_VIEWER_SUPP` specifically pertains to the profiling and analysis capabilities of the simulation process within

The software application published by Aldec that contains the feature/module/file called 'RIVIERA_PSL_SUPPORT' is **Riviera-PRO**. Riviera-PRO is a simulation and verification tool aimed at enhancing the design and verification process for complex hardware designs, including digital and mixed-signal systems. **RIVIERA_PSL_SUPPORT** refers to the support for Property Specification Language (PSL) within Riviera-PRO. PSL is a standard for

The software application published by Aldec that includes the 'RIVIERA_SIGNAL_AGENT' feature is called **Riviera-PRO**. **RIVIERA_SIGNAL_AGENT** is a module within Riviera-PRO that is used for advanced debugging and analysis of signals within digital designs. It provides capabilities for monitoring, controlling, and analyzing signals in real-time during simulation. This feature aids design engineers in understanding and validating the behavior

The software application published by Aldec that includes a feature/module/file called 'RIVIERA_SV_VERIFICATION' is **Riviera-PRO**. **RIVIERA_SV_VERIFICATION** is a verification environment that supports SystemVerilog and is used for functional verification of digital designs. It provides advanced simulation capabilities, including support for various methodologies like UVM (Universal Verification Methodology), enabling users to create and use

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The software application published by Aldec that includes the feature/module/file called **RIVIERA_SVA_SUPPORT** is **Riviera-PRO**. Riviera-PRO is a comprehensive simulation and verification tool for hardware design, particularly for users of VHDL, Verilog, SystemVerilog, and other hardware description languages. **RIVIERA_SVA_SUPPORT** refers to support for **SystemVerilog Assertions (SVA)** within the Riviera-PRO toolset. SystemVerilog

The software application published by Aldec that includes a feature/module/file called 'RIVIERA_SVA_SUPPORT_2021.0331' is **Riviera-PRO**. Riviera-PRO is a comprehensive verification environment designed for hardware description languages such as VHDL and Verilog, and it supports several advanced verification methodologies. The 'RIVIERA_SVA_SUPPORT_2021.0331' likely refers to a specific version or update related to SystemVerilog Assertions

The software application published by Aldec that includes the feature or module called `RIVIERA_SYSTEM_VERILOG_SUPPORT` is **Riviera-PRO**. `RIVIERA_SYSTEM_VERILOG_SUPPORT` refers to the Verilog support module in Riviera-PRO, which is a comprehensive simulation and debugging environment for system design using hardware description languages (HDLs) such as Verilog and VHDL. This feature enables users to simulate and verify Verilog designs,

The software application published by Aldec that has a feature called **RIVIERA_SYSTEMC_SUPPORT** is **Riviera-PRO**. **RIVIERA_SYSTEMC_SUPPORT** is a component of Riviera-PRO that provides support for SystemC, a system-level modeling language used primarily in system-on-chip (SoC) design. This support includes functionalities for compiling, simulating, and debugging SystemC code, enabling engineers to effectively work on high-level synthesis

The software application published by Aldec that includes a feature called "RIVIERA_UNIFIED_COVERAGE" is **Riviera-PRO**. **RIVIERA_UNIFIED_COVERAGE** is a coverage analysis module within Riviera-PRO, designed for digital design verification and analysis. This feature allows users to collect and analyze coverage data during simulation runs. It helps engineers assess how effectively their tests exercise the design under test, identifying

The software application published by Aldec that includes the feature or module called **RIVIERA_VERILOG_SIMULATION** is **Riviera-PRO**. Rivera-PRO is a sophisticated simulation and debug environment for Verilog, VHDL, and SystemVerilog. **RIVIERA_VERILOG_SIMULATION** refers to the capability within Riviera-PRO that specifically handles the simulation of Verilog designs. This module allows users to perform simulation tasks on Verilog code,

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The software application published by Aldec that includes the feature or module named `RIVIERA_VERILOG_SIMULATION_2021.0331` is **Riviera-PRO**. Riviera-PRO is a comprehensive simulation and verification environment for digital designs, specifically tailored for SystemVerilog, Verilog, VHDL, and other hardware description languages. The component `RIVIERA_VERILOG_SIMULATION_2021.0331` likely refers to a specific version or build of the Verilog

The software application published by Aldec that includes the feature or module called 'RIVIERA_VERILOG_SIMULATION_LV' is **Riviera-PRO**. This is a powerful simulation and verification tool for digital designs that supports various hardware description languages, including Verilog, VHDL, and SystemVerilog. **RIVIERA_VERILOG_SIMULATION_LV** specifically pertains to the simulation capabilities for Verilog designs within the Riviera-PRO

The software application published by Aldec that includes a feature or module called **RIVIERA_VHDL_DSE** is **RIVIERA-PRO**. RIVIERA-PRO is a comprehensive simulation and verification tool for digital designs, capable of handling VHDL, Verilog, SystemVerilog, and mixed-language simulations. **RIVIERA_VHDL_DSE** stands for **RIVIERA VHDL Design Space Exploration**. This module is used for enhancing the design and verification process by allowing

The software application published by Aldec that includes the feature or module called 'RIVIERA_VHDL_DSE_2021.0331' is **Riviera-PRO**. Riviera-PRO is a comprehensive simulation and advanced debugging tool for VHDL, Verilog, and SystemVerilog. The specific term 'RIVIERA_VHDL_DSE_2021.0331' likely refers to a specific version or release of a feature related to VHDL simulation or design space exploration (DSE) within the Riviera-PRO environment,